Memory-Centric Computing

Time and Location:

Computing is bottlenecked by data. Large amounts of application data overwhelm the storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications' performance, efficiency, and scalability are bottlenecked by data movement. In this talk, we describe three major shortcomings of modern computers in terms of 1) dealing with data, 2) taking advantage of vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent computing architecture should be designed to handle data well. We posit that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give examples of how to exploit these principles to design a much more efficient and higher performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising directions: 1) processing using memory, which exploits the fundamental operational
properties of memory chips to perform massively-parallel computation in memory, with low-cost changes, 2) processing near memory, which
integrates sophisticated additional processing capability in memory chips, the logic layer of 3D-stacked technologies, or memory controllers to enable near-memory computation with high memory bandwidth and low memory latency. We show both types of architectures can enable order(s) of magnitude improvements in performance and energy consumption of many important workloads, such as artificial intelligence, machine learning, graph analytics, database systems, video processing, climate modeling, genome analysis. We discuss how to enable adoption of such fundamentally more intelligent architectures, which are key to efficiency, performance, and sustainability. We conclude with some research opportunities in and guiding principles for future computing architecture and system designs.

An accompanying overview of modern memory-centric computing ideas &
systems can be found at https://arxiv.org/pdf/2012.03112 ("A Modern Primer on Processing in Memory", updated February 2025).

A shorter invited paper from IMW 2025 is at https://arxiv.org/pdf/2505.00458 (“Memory-Centric Computing: Solving Computing’s Memory Problem”, May 2025)

Speaker Bio: 

Onur Mutlu is a Professor of ECE & CSE at NYU and a Professor of Computer Science at ETH Zurich. He previously held the William D. and
Nancy W. Strecker Early Career Professorship at Carnegie Mellon University. His research interests are in computer architecture, computing systems, hardware security, memory & storage systems, and bioinformatics, with a major focus on designing fundamentally
energy-efficient, high-performance, and robust computing systems. He started the Computer Architecture Group at Microsoft Research
(2006-2009), and held product, research and visiting positions at Intel Corporation, Advanced Micro Devices, VMware, Google, Microsoft,
and Stanford University. He received various honors for his research, including recently the 2026 Intel Hardware Security Test of Time Award
and the 2025 IEEE Computer Society Harry H. Goode Memorial Award “for seminal contributions to computer architecture research and practice,
especially in memory systems.” He is an AAAS Fellow, ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. He enjoys teaching, mentoring, and enabling & democratizing access to high-quality research and education. He has supervised 27 PhD
graduates, many of whom received major dissertation awards, 20 postdoctoral trainees, and more than 70 Master’s and Bachelor’s
students. His computer architecture and digital design course lectures and materials are freely available on YouTube and his research group
makes a wide variety of artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.

Note: In-person attendance only available to those with active NYU ID cards.